82NM10 Datasheet, PDF (386/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-121.PIC Registers (LPC I/F—D31:F0)
Port
Aliases
Register Name
21h
A0h
A1h
4D0h
4D1h
25h, 29h,
2Dh, 31h,
35h, 39h,
3Dh
A4h, A8h,
ACh, B0h,
B4h, B8h,
BCh
A5h, A9h,
ADh, B1h,
B5h, B9h,
BDh
–
–
Master PIC ICW2 Init. Cmd Word 2
Master PIC ICW3 Init. Cmd Word 3
Master PIC ICW4 Init. Cmd Word 4
Master PIC OCW1 Op Ctrl Word 1
Slave PIC ICW1 Init. Cmd Word 1
Slave PIC OCW2 Op Ctrl Word 2
Slave PIC OCW3 Op Ctrl Word 3
Slave PIC ICW2 Init. Cmd Word 2
Slave PIC ICW3 Init. Cmd Word 3
Slave PIC ICW4 Init. Cmd Word 4
Slave PIC OCW1 Op Ctrl Word 1
Master PIC Edge/Level Triggered
Slave PIC Edge/Level Triggered
Default
Value
Undefined
Undefined
01h
00h
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
00h
00h
Type
WO
WO
WO
R/W
WO
WO
WO
WO
WO
WO
R/W
R/W
R/W
Note:
Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section (Chapter 5.9 - Volume 1).
13.4.2
ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 20h
Slave Controller – A0h
Default Value: All bits undefined
Attribute:
Size:
WO
8 bit /controller
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
Bit
Description
7:5 ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.
000 = Should be programmed to “000”
4 ICW/OCW Select — WO.
1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4
sequence.
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