82NM10 Datasheet, PDF (132/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Figure 5-12. Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
If COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an
internal IRQ13, nor will the write to F0h generate IGNNE#.
5.13.1.4
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Table 5-51.
Table 5-51.NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally,
externally via SERR# signal, or via
message from CPU)
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
IOCHK# goes active via SERIRQ# stream Can instead be routed to generate an SCI, through
(ISA system Error)
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#)
Chipset power management logic controls these active-low signals. Refer to
Section 5.14 for more information on the functionality of these signals.
Note:
CPU Sleep (CPUSLP#) is supported only on Nettop platforms.
5.13.1.6
CPU Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. This signal represents a
logical AND of chipset’s PWROK and VRMPWRGD signals.
5.13.1.7
Deeper Sleep (DPSLP#)
This active-low signal controls the internal gating of the processor’s core clock. This
signal asserts before and deasserts after the STP_CPU# signal to effectively stop the
processor’s clock (internally) in the states in which STP_CPU# can be used to stop the
processor’s clock externally.
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