82NM10 Datasheet, PDF (599/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Bit
Description
0
Controller Reset # — R/W.
0 = Writing a 0 to this bit causes the Intel High Definition Audio controller to be reset.
All state machines, FIFOs, and non-resume well memory mapped configuration
registers (not PCI configuration registers) in the controller will be reset. The Intel
High Definition Audio link RESET# signal will be asserted, and all other link
signals will be driven to their default values. After the hardware has completed
sequencing into the reset state, it will report a 0 in this bit. Software must read a
0 from this bit to verify the controller is in reset.
1 = Writing a 1 to this bit causes the controller to exit its reset state and deassert the
Intel High Definition Audio link RESET# signal. Software is responsible for setting/
clearing this bit such that the minimum Intel High Definition Audio link RESET#
signal assertion pulse width specification is met. When the controller hardware is
ready to begin operation, it will report a 1 in this bit. Software must read a 1 from
this bit before accessing any controller registers. This bit defaults to a 0 after
Hardware reset, therefore, software needs to write a 1 to this bit to begin
operation.
NOTES:
1.
The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0
before writing a 0 to this bit in order to assure a clean re-start.
2.
When setting or clearing this bit, software must ensure that minimum link
timing requirements (minimum RESET# assertion time, etc.) are met.
3.
When this bit is 0 indicating that the controller is in reset, writes to all Intel
High Definition Audio memory mapped registers are ignored as if the device is
not present. The only exception is this register itself. The Global Control
register is write-able as a DWord, Word, or Byte even when CRST# (this bit) is
0 if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is
active. If Byte Enable 0 is not active, writes to the Global Control register will
18.2.7
WAKEEN—Wake Enable Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 0Ch
Attribute:
R/W
Default Value:
0000hSize:16 bits
Bit
Description
15:3
2:0
Reserved.
SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may
generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is
enabled to generate a wake.
Bit 0 is used for SDI0
Bit 1 is used for SDI1
Bit 2 is used for SDI2
NOTE: These bits are in the resume well and only cleared on a power on reset.
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
Datasheet
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