82NM10 Datasheet, PDF (17/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

16.2
16.1.25PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F7) ............................................................................ 530
16.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F7).................................................. 530
16.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7) ......................................... 531
16.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F7) ............................................................................ 533
16.1.29ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F7) ............................................................................ 534
Memory-Mapped I/O Registers .......................................................................... 534
16.2.1 Host Controller Capability Registers ........................................................ 535
16.2.2 Host Controller Operational Registers ...................................................... 537
16.2.3 USB 2.0-Based Debug Port Register ........................................................ 551
17 SMBus Controller Registers (D31:F3)..................................................................... 555
17.1
17.2
PCI Configuration Registers (SMBUS—D31:F3) .................................................... 555
17.1.1 VID—Vendor Identification Register (SMBUS—D31:F3) .............................. 555
17.1.2 DID—Device Identification Register (SMBUS—D31:F3) .............................. 556
17.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3) ................................. 556
17.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3) ....................................... 557
17.1.5 RID—Revision Identification Register (SMBUS—D31:F3) ............................ 557
17.1.6 PI—Programming Interface Register (SMBUS—D31:F3) ............................. 558
17.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3) ..................................... 558
17.1.8 BCC—Base Class Code Register (SMBUS—D31:F3).................................... 558
17.1.9 SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3) ................................................................................ 558
17.1.10SVID — Subsystem Vendor Identification Register
(SMBUS—D31:F2/F4) ........................................................................... 559
17.1.11SID — Subsystem Identification Register
(SMBUS—D31:F2/F4) ........................................................................... 559
17.1.12INT_LN—Interrupt Line Register (SMBUS—D31:F3)................................... 559
17.1.13INT_PN—Interrupt Pin Register (SMBUS—D31:F3) .................................... 559
17.1.14HOSTC—Host Configuration Register (SMBUS—D31:F3)............................. 560
SMBus I/O Registers ........................................................................................ 560
17.2.1 HST_STS—Host Status Register (SMBUS—D31:F3) ................................... 561
17.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3).................................. 563
17.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3) ............................. 565
17.2.4 XMIT_SLVA—Transmit Slave Address Register
(SMBUS—D31:F3) ................................................................................ 565
17.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3) .................................... 565
17.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3) .................................... 565
17.2.7 Host_BLOCK_DB—Host Block Data Byte Register
(SMBUS—D31:F3) ................................................................................ 566
17.2.8 PEC—Packet Error Check (PEC) Register
(SMBUS—D31:F3) ................................................................................ 566
17.2.9 RCV_SLVA—Receive Slave Address Register
(SMBUS—D31:F3) ................................................................................ 567
17.2.10SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3) ....................... 567
17.2.11AUX_STS—Auxiliary Status Register (SMBUS—D31:F3) ............................. 567
17.2.12AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3) ............................ 568
17.2.13SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBUS—D31:F3) ................................................................................ 568
Datasheet
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