82NM10 Datasheet, PDF (427/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
31:16
15
14
13
Description
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16
corresponds to GPIO0.
Reserved
USB4_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB4_STS bit to generate a wake event. The
USB4_STS bit is set anytime USB UHCI controller #4 signals a wake event.
Break events are handled via the USB interrupt.
PME_B0_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an
SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from
S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
12
USB3_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The
USB3_STS bit is set anytime USB UHCI controller #3 signals a wake event.
Break events are handled via the USB interrupt.
11
PME_EN — R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered via
SLP_EN, but not power button override).
10
(Nettop
Only)
Reserved
10
(Netbook
Only)
BATLOW_EN — R/W. (Netbook Only)
0 = Disable.
1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the
SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal
from inhibiting the wake event.
9
PCI_EXP_EN — R/W.
0 = Disable SCI generation upon PCI_EXP_STS bit being set.
1 = Enables Chipset to cause an SCI when PCI_EXP_STS bit is set. This is used to
allow the PCI Express* ports, including the link to the (G)MCH/CPU, to cause an
SCI due to wake/PME events.
9
Reserved. Must be programmed to 0.
8
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not
affected by a hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7
Reserved
Datasheet
427