82NM10 Datasheet, PDF (134/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
— Hardware Override to throttle processor performance if system too hot
— SCI and SMI# Generation
• PCI PME# signal for Wake Up from Low-Power states
• System Clock Control
— (Netbook Only) ACPI C2 state: Stop Grant (using STPCLK# signal) halts
processor’s instruction stream
— (Netbook Only) ACPI C3 State: Ability to halt processor clock (but not memory
clock)
— (Netbook Only) ACPI C4 State: Ability to lower processor voltage.
— (Netbook Only) CLKRUN# Protocol for PCI Clock Starting/Stopping
• System Sleep State Control
— ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor’s instruction
stream (only STPCLK# active, and CPUSLP# optional)
— ACPI S3 state — Suspend to RAM (STR)
— ACPI S4 state — Suspend-to-Disk (STD)
— ACPI G2/S5 state — Soft Off (SOFF)
— Power Failure Detection and Recovery
• Streamlined Legacy Power Management for APM-Based Systems
5.14.2 Chipset and System Power States
Table 5-53 shows the power states defined for CHIPSET-based platforms. The state
names generally match the corresponding ACPI states.
Table 5-53.General Power States for Systems Using Chipset (Sheet 1 of 2)
State/
Substates
G0/S0/C0
G0/S0/C1
G0/S0/C2
(Netbook
Only)
G0/S0/C3
(Netbook
Only)
Legacy Name / Description
Full On: Processor operating. Individual devices may be shut down to save
power. The different processor operating levels are defined by Cx states, as
shown in Table 5-54. Within the C0 state, Chipset can throttle the processor
using the STPCLK# signal to reduce power consumption. The throttling can be
initiated by software or by the operating system or BIOS.
Auto-Halt: Processor has executed an AutoHalt instruction and is not executing
code. The processor snoops the bus and maintains cache coherency.
Stop-Grant: The STPCLK# signal goes active to the processor. The processor
performs a Stop-Grant cycle, halts its instruction stream, and remains in that
state until the STPCLK# signal goes inactive. In the Stop-Grant state, the
processor snoops the bus and maintains cache coherency.
Stop-Clock: The STPCLK# signal goes active to the processor. The processor
performs a Stop-Grant cycle, halts its instruction stream. Chipset then asserts
DPSLP# followed by STP_CPU#, which forces the clock generator to stop the
processor clock. This is also used for Intel SpeedStep^® technology support.
Accesses to memory (by graphics, PCI, or internal units) is not permitted while in
a C3 state.
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Datasheet