82NM10 Datasheet, PDF (510/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
19
18
17
16
15
14
13
12:8
7:5
Interlock Switch Attached to Port (ISP) — R/WO. When interlock switches are supported in the
platform (CAP.SIS [ABAR+00h:bit 28] set), this indicates whether this particular port has an interlock
switch attached. This bit can be used by system software to enable such features as aggressive power
management, as disconnects can always be detected regardless of PHY state with an interlock switch.
When this bit is set, it is expected that HPCP (bit 18) in this register is also set.
The Chipset takes no action on the state of this bit – it is for system software only. For example, if this
bit is cleared, and an interlock switch toggles, the Chipset still treats it as a proper interlock switch
event.
Note that these bits are not reset on a HBA reset.
Hot Plug Capable Port (HPCP) — R/WO.
0 = Port is not capable of Hot-Plug.
1 = Port is Hot-Plug capable.
This indicates whether the platform exposes this port to a device which can be Hot-Plugged. SATA by
definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it
may be screwed into the chassis, for example). This bit can be used by system software to indicate a
feature such as “eject device” to the end-user. The Chipset takes no action on the state of this bit - it is
for system software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the Chipset
still treats it as a proper Hot-Plug event.
Note that these bits are not reset on a HBA reset.
Port Multiplier Attached (PMA) — RO / R/W. When this bit is set, a port multiplier is attached to the
Chipset for this port. When cleared, a port multiplier is not attached to this port.
This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when CAP.PMS = 1.
NOTE: Port Multiplier not supported by Chipset.
Port Multiplier FIS Based Switching Enable (PMFSE) — RO. The Chipset does not support FIS-based
switching.
NOTE: Port Multiplier not supported by Chipset.
Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are running. See
section 5.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the
Chipset.
FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the port is running. See
section 12.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by the
Chipset.
Interlock Switch State (ISS) — RO. For systems that support interlock switches (via CAP.SIS
[ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP in this register), this bit indicates
the current state of the interlock switch. A 0 indicates the switch is closed, and a 1 indicates the switch
is opened.
For systems that do not support interlock switches, or if an interlock switch is not attached to this port,
this bit reports 0.
Current Command Slot (CCS) — RO. Indicates the current command slot the Chipset is processing.
This field is valid when the ST bit is set in this register, and is constantly updated by the Chipset. This
field can be updated as soon as the Chipset recognizes an active command slot, or at some point soon
after when it begins processing the command.
This field is used by software to determine the current command issue location of the Chipset. In
queued mode, software shall not use this field, as its value does not represent the current command
being executed. Software shall only use PxCI and PxSACT when running queued commands.
Reserved
510
Datasheet