82NM10 Datasheet, PDF (67/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Pin States
Table 3-26.Power Plane and States for Output and I/O Signals (Sheet 2 of 4)
Signal Name
Power
Plane
During
PLTRST#⁶ /
RSMRST#⁷
Immediately
after
PLTRST#⁶ /
RSMRST#⁷
C3/C4
S1
S3_COLD13
S4/
S5
SATA[0]TXP,
SATA[0]TXN
SATA[1]TXP,
SATA[1]TXN
SATALED#
SATARBIAS
Core
Core
Core
PIRQ[A:D]#,
PIRQ[H:E]# /
GPIO[5:2]
SERIRQ
Core
Core
USBP[7:0][P,N]
USBRBIAS
Suspend
Suspend
OC[7:5]#/
GP[31:29]
Suspend
PLTRST#
SLP_S3#
SLP_S4#
SLP_S5#
STP_PCI#
STP_CPU#
SUS_STAT# /
LPCPD#
DPRSLPVR
DPRSTP#
SUSCLK
Suspend
Suspend
Suspend
Suspend
Core
Core
Suspend
Core
Core
Suspend
SATA Interface
High-Z
High-Z
Defined Defined
Off
Off
High-Z
High-Z
High-Z
Defined Defined
Off
Off
High-Z
Defined Defined
Off
Off
Interrupts
High-Z
High-Z
Defined High-Z
Off
Off
High-Z
High-Z
USB Interface
Low
High-Z
Low
High-Z
Input
Input
Running High-Z
Off
Off
Low
Defined
Low
Defined
Driven Driven
Low
Defined
Driven
Low
Define
d
Driven
Power Management
Low
High
Low
Low
High
High
Low
High
High
High
High
High
Low
High
High
High
High
High
Defined
Low
High
High
High
High
High
High
High
High
Low
High
Low
Low
High
Low/
High⁵
High
Low/
High⁵
High
Running
Low
Low
High
High
Low
Low
Low
Off
Off
Low
Low
Low
Low¹⁰
Low
Low
Low
Off
Off
Datasheet
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