82NM10 Datasheet, PDF (130/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-49.Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)
Bit Name
Register
Location
Bit(s)
RI_EN
General Purpose
PMBase + 2Ch
8
Event 0 Enables
Register (GPE0_EN)
NEWCENTURY_STS
TCO1 Status Register TCOBase + 04h
7
(TCO1_STS)
Intruder Detect
TCO2 Status Register TCOBase + 06h
0
(INTRD_DET)
(TCO2_STS)
Top Swap (TS)
Backed Up Control
Chipset Config
0
Register (BUC)
Registers:Offset 3414h
Default
State
0
0
0
X
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
Note:
The GPI strap technique to clear CMOS requires multiple steps to implement. The
system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again.
Warning: Clearing CMOS, using a jumper on VccRTC, must not be implemented.
5.13
Processor Interface (D31:F0)
Chipset interfaces to the processor with a variety of signals
• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,
IGNNE#, CPUSLP# (supported only on Nettop platforms), CPUPWRGD
• Standard Input from processor: FERR#
• Intel SpeedStep^® technology output to processor: CPUPWRGOOD (In Netbook
configurations)
Most Chipset outputs to the processor use standard buffers. Chipset has separate
V_CPU_IO signals that are pulled up at the system level to the processor voltage, and
thus determines VOH for the outputs to the processor.
5.13.1
Processor Interface Signals
This section describes each of the signals that interface between Chipset and the
processor(s). Note that the behavior of some signals may vary during processor reset,
as the signals are used for frequency strapping.
5.13.1.1
A20M# (Mask A20)
The A20M# signal is active (low) when both of the following conditions are true:
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