82NM10 Datasheet, PDF (540/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
Bit
Description
14 Periodic Schedule Status ⎯ RO. This bit reports the current real status of the Periodic
Schedule.
0 = Status of the Periodic Schedule is disabled. (Default)
1 = Status of the Periodic Schedule is enabled.
13
12
11:6
5
4
NOTE: The Host controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit
(D29:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit
and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0).
Reclamation ⎯ RO. 0=Default. This read-only status bit is used to detect an empty
asynchronous schedule. The operational model and valid transitions for this bit are
described in Section 4 of the EHCI Specification.
HCHalted ⎯ RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the
Run/Stop bit being set to 0, either by software or by the Host controller hardware
(e.g., internal error). (Default)
Reserved
Interrupt on Async Advance — R/WC. 0=Default. System software can force the host
controller to issue an interrupt the next time the host controller advances the
asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit
(D29:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the
assertion of that interrupt source.
Host System Error — R/WC.
0 = No serious error occurred during a host system access involving the Host controller
module
1 = The Host controller sets this bit to 1 when a serious error occurs during a host
system access involving the Host controller module. A hardware interrupt is
generated to the system. Memory read cycles initiated by the EHC that receive any
status other than Successful will result in this bit being set.
When this error occurs, the Host controller clears the Run/Stop bit in the
USB2.0_CMDregister (D29:F7:CAPLENGTH + 20h, bit 0) to prevent further
execution of the scheduled TDs. A hardware interrupt is generated to the system (if
enabled in the Interrupt Enable Register).
3 Frame List Rollover — R/WC.
0 = No Frame List Index rollover from its maximum value to 0.
1 = The Host controller sets this bit to a 1 when the Frame List Index (see Section) rolls
over from its maximum value to 0. Since the Chipset only supports the 1024-entry
Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles.
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Datasheet