82NM10 Datasheet, PDF (624/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
8 SERR# Enable (SEE) — R/W.
0 = Disable.
1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.
7 Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification.
6 Parity Error Response (PER) — R/W.
0 = Disable.
1 = Indicates that the device is capable of reporting parity errors as a master on the
backbone.
5 VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification.
4 Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base
Specification.
3 Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification.
2 Bus Master Enable (BME) — R/W.
0 = Disable. All cycles from the device are master aborted
1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI
Express* device.
1 Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
registers are master aborted on the backbone.
1 = Enable. Allows memory cycles within the range specified by the memory base and
limit registers can be forwarded to the PCI Express device.
0 I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers
are master aborted on the backbone.
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
registers can be forwarded to the PCI Express device.
19.1.4
PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 06h–07h
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15 Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Root port received a command or data from the backbone with a parity error. This
is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
14 Signaled System Error (SSE) — R/WC.
0 = No system error signaled.
1 = Root port signaled a system error to the internal SERR# logic.
13 Received Master Abort (RMA) — R/WC.
0 = Root port has not received a completion with unsupported request status from the
backbone.
1 = Root port received a completion with unsupported request status from the
backbone.
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Datasheet