82NM10 Datasheet, PDF (400/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.6.2.3
Bit
Description
4 Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but
not on any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
3 Square Wave Enable (SQWE) — R/W. This bit serves no function in the Chipset. It is
left in this register bank to provide compatibility with the Motorola 146818B. The
Chipset has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.
2 Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation.
This bit is not affected by RSMRST# nor any other reset signal.
0 = BCD
1 = Binary
1 Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is
not affected by RSMRST# nor any other reset signal.
0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and
PM as one.
1 = Twenty-four hour mode.
0 Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per
year. The days for the hour adjustment are those specified in United States federal law
as of 1987, which is different than previous years. This bit is not affected by RSMRST#
nor any other reset signal.
0 = Daylight Savings Time updates do not occur.
1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to
3:00:00 AM.
b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it
is changed to 1:00:00 AM. The time must increment normally for at least two
update cycles (seconds) previous to these conditions for the time change to occur
properly.
RTC_REGC—Register C (Flag Register)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Ch
Attribute:
00U00000 (U: Undefined) Size:
No
Power Well:
RO
8-bit
RTC
Writes to Register C have no effect.
Bit
Description
7
Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE).
This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST#
or a read of Register C.
6 Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of
Register C.
0 = If no taps are specified via the RS bits in Register A, this flag will not be set.
1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is
1.
400
Datasheet