82NM10 Datasheet, PDF (669/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Serial Peripheral Interface (SPI)
21.1.5
BBAR—BIOS Base Address Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 50h
Attribute:
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31:24 Reserved.
23:8
Bottom of System Flash — R/W. This field determines the bottom of the System
BIOS. The Chipset will not run programmed commands nor memory reads whose
address field is less than this value. This field corresponds to bits 23:8 of the 3-byte
address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential
SPI address.
NOTE: Software must always program 1s into the upper, Don’t Care, bits of this field
based on the flash size. Hardware does not know the size of the flash array and
relies upon the correct programming by software. The default value of 0000h
results in all cycles allowed.
NOTE: In the event that this value is programmed below some of the BIOS Memory
segments, described above, this protection policy takes precedence.
7:0 Reserved
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
21.1.6
PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 54h
Attribute:
R/W
Default Value:
0004hSize:16 bits
Bit
Description
15:8 Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
7:0 Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
Datasheet
669