82NM10 Datasheet, PDF (73/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset and System Clock Domains
4 Chipset and System Clock
Domains
Table 4-28 shows the system clock domains. Figure 4-4 and Figure 4-5 show the
assumed connection of the various system components, including the clock generator
in Nettop and Netbook systems. For complete details of the system clocking solution,
refer to the system’s clock generator component specification.
Table 4-28.Chipset and System Clock Domains
Clock Domain Frequency
Source
Usage
Chipset
SATA_CLKP,
SATA_CLKN
Chipset
DMI_CLKP,
DMI_CLKN
Chipset
PCICLK
System PCI
Chipset
CLK48
Chipset
CLK14
LAN_CLK
SPI_CLK
100 MHz
Main Clock Differential clock pair used for SATA.
Generator
100 MHz
Main Clock Differential clock pair used for DMI.
Generator
33 MHz
33 MHz
48.000 MHz
14.31818
MHz
5 to 50 MHz
17.86 MHz
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
LAN Connect
Component
ICH
Free-running PCI Clock to Chipset. This clock
remains on during S0 and S1 (in Nettop) state,
and is expected to be shut off during S3 or
below in Nettop configurations or S1 or below in
Netbook configurations.
PCI Bus, LPC I/F. These only go to external PCI
and LPC devices. Will stop based on CLKRUN#
(and STP_PCI#) in Netbook configurations.
Super I/O, USB controllers. Expected to be shut
off during S3 or below in Nettop configurations
or S1 or below in Netbook configurations.
Used for ACPI timer and Multimedia Timers.
Expected to be shut off during S3 or below in
Nettop configurations or S1 or below in Netbook
configurations.
Generated by the LAN Connect component.
Expected to be shut off during S3 or below in
Nettop configurations or S1 or below in Netbook
configurations.
Generated by the LAN Connect component.
Expected to be shut off during S3 or below in
Nettop configurations or S1 or below in Netbook
configurations.
Datasheet
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