82NM10 Datasheet, PDF (3/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Contents
1 Introduction ............................................................................................................ 30
1.1 Intel NM10 Family Express Chipset Feature Support ............................................... 31
1.2 Content Layout ................................................................................................. 34
1.3 Functions and capabilities ................................................................................... 36
2 Signal Description.................................................................................................... 43
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
Direct Media Interface (DMI) to Host Controller ..................................................... 45
PCI Express* .................................................................................................... 45
Platform LAN Connect Interface........................................................................... 45
EEPROM Interface ............................................................................................. 46
Firmware Hub Interface...................................................................................... 46
PCI Interface .................................................................................................... 47
Serial ATA Interface........................................................................................... 49
LPC Interface .................................................................................................... 50
Interrupt Interface ............................................................................................ 50
USB Interface ................................................................................................... 51
Power Management Interface.............................................................................. 52
Processor Interface............................................................................................ 54
SMBus Interface................................................................................................ 56
System Management Interface ............................................................................ 56
Real Time Clock Interface ................................................................................... 56
Other Clocks ..................................................................................................... 57
Miscellaneous Signals......................................................................................... 57
Intel HD Audio Link............................................................................................ 58
Serial Peripheral Interface (SPI) .......................................................................... 59
General Purpose I/O Signals ............................................................................... 59
Power and Ground ............................................................................................. 60
Pin Straps ........................................................................................................ 61
2.22.1 Functional Straps ................................................................................... 61
2.22.2 External RTC Circuitry ............................................................................. 63
Device and Revision ID Table .............................................................................. 64
3 Pin States ................................................................................................................ 65
3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 65
3.2 Output and I/O Signals Planes and States............................................................. 66
3.3 Power Planes for Input Signals ............................................................................ 71
4
Chipset and System Clock Domains......................................................................... 74
5 Functional Description ............................................................................................. 76
5.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 76
5.1.1 PCI Bus Interface ................................................................................... 76
5.1.2 PCI Bridge As an Initiator ........................................................................ 76
5.1.3 Parity Error Detection and Generation ....................................................... 78
5.1.4 PCIRST# ............................................................................................... 79
5.1.5 Peer Cycles............................................................................................ 79
5.1.6 PCI-to-PCI Bridge Model .......................................................................... 80
5.1.7 IDSEL to Device Number Mapping............................................................. 80
5.1.8 Standard PCI Bus Configuration Mechanism ............................................... 80
Datasheet
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