82NM10 Datasheet, PDF (6/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

5.20
5.21
5.22
5.23
5.19.4 Data Encoding and Bit Stuffing ............................................................... 187
5.19.5 Packet Formats .................................................................................... 187
5.19.6 USB 2.0 Interrupts and Error Conditions .................................................. 187
5.19.7 USB 2.0 Power Management .................................................................. 188
5.19.8 Interaction with UHCI Host Controllers..................................................... 190
5.19.9 USB 2.0 Legacy Keyboard Operation ....................................................... 193
5.19.10USB 2.0 Based Debug Port ..................................................................... 193
SMBus Controller (D31:F3) ............................................................................... 199
5.20.1 Host Controller ..................................................................................... 199
5.20.2 Bus Arbitration ..................................................................................... 204
5.20.3 Bus Timing .......................................................................................... 205
5.20.4 Interrupts / SMI# ................................................................................. 205
5.20.5 SMBALERT#......................................................................................... 207
5.20.6 SMBus CRC Generation and Checking ...................................................... 207
5.20.7 SMBus Slave Interface........................................................................... 207
Intel HD Audio Overview................................................................................... 213
Serial Peripheral Interface (SPI) ........................................................................ 214
5.22.1 Flash Device Configurations ................................................................... 214
5.22.2 SPI Device Compatibility Requirements.................................................... 214
5.22.3 Chipset Compatible Command Set .......................................................... 215
5.22.4 Flash Protection.................................................................................... 216
Feature Capability Mechanism ........................................................................... 217
6 Ballout Definition ................................................................................................... 218
6.1 Chipset Ballout, Signal, and Mechanical Document ............................................... 218
6.2 Chipset Ballout ................................................................................................ 218
7 Chipset Package Information ................................................................................. 225
8 Electrical Characteristics........................................................................................ 227
8.1 Thermal Specifications...................................................................................... 227
8.2 Absolute Maximum Ratings ............................................................................... 227
8.3 DC Characteristics ........................................................................................... 228
8.4 AC Characteristics............................................................................................ 235
8.5 Timing Diagrams ............................................................................................. 244
9 Register and Memory Mapping ............................................................................... 258
9.1 PCI Devices and Functions ................................................................................ 258
9.2 PCI Configuration Map ...................................................................................... 259
9.3 I/O Map.......................................................................................................... 260
9.3.1 Fixed I/O Address Ranges ...................................................................... 260
9.3.2 Variable I/O Decode Ranges ................................................................... 262
9.4 Memory Map ................................................................................................... 264
9.4.1 Boot-Block Update Scheme .................................................................... 265
10 Chipset Configuration Registers ............................................................................. 267
10.1
Chipset Configuration Registers (Memory Space) ................................................. 267
10.1.1 VCH—Virtual Channel Capability Header Register ...................................... 269
10.1.2 VCAP1—Virtual Channel Capability #1 Register ......................................... 269
10.1.3 VCAP2—Virtual Channel Capability #2 Register ......................................... 270
10.1.4 PVC—Port Virtual Channel Control Register............................................... 270
10.1.5 PVS—Port Virtual Channel Status Register................................................ 270
10.1.6 V0CAP—Virtual Channel 0 Resource Capability Register.............................. 270
10.1.7 V0CTL—Virtual Channel 0 Resource Control Register ................................. 271
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