82NM10 Datasheet, PDF (377/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.2.3
13.2.4
DMAMEM_LP—DMA Memory Low Page Registers
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0 = 87h; Ch. #1 = 83h
Ch. #2 = 81h; Ch. #3 = 82h
Ch. #5 = 8Bh; Ch. #6 = 89h
Ch. #7 = 8Ah;
Attribute:
Undefined
Size:
No
Power Well:
R/W
8-bit
Core
Bit
Description
7:0 DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction
with the DMA controller's Current Address Register to define the complete 24-bit
address for the DMA channel. This register remains static throughout the DMA transfer.
Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is
replaced by the bit 15 shifted out from the current address register.
DMACMD—DMA Command Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 08h;
Ch. #4–7 = D0h
Undefined
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:5 Reserved. Must be 0.
4 DMA Group Arbitration Priority — WO. Each channel group is individually assigned
either fixed or rotating arbitration priority. At part reset, each group is initialized in
fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
3 Reserved. Must be 0.
2 DMA Channel Group Enable — WO. Both channel groups are enabled following part
reset.
0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is
cascaded through channel 4.
1:0 Reserved. Must be 0.
Datasheet
377