82NM10 Datasheet, PDF (375/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-120.DMA Registers (Sheet 2 of 2)
Port
81h
82h
83h
84h–86h
87h
88h
89h
8Ah
8Bh
8Ch–8Eh
8Fh
C0h
C2h
C4h
C6h
C8h
CAh
CCh
CEh
D0h
D4h
D6h
D8h
DAh
DCh
DEh
Alias
Register Name
91h
—
93h
94h–96h
97h
98h
99h
9Ah
9Bh
9Ch–9Eh
9Fh
C1h
C3h
C5h
C7h
C9h
CBh
CDh
CFh
D1h
D5h
D7h
D9h
DBh
DDh
DFh
Channel 2 DMA Memory Low Page
Channel 3 DMA Memory Low Page
Channel 1 DMA Memory Low Page
Reserved Pages
Channel 0 DMA Memory Low Page
Reserved Page
Channel 6 DMA Memory Low Page
Channel 7 DMA Memory Low Page
Channel 5 DMA Memory Low Page
Reserved Page
Refresh Low Page
Channel 4 DMA Base & Current Address
Channel 4 DMA Base & Current Count
Channel 5 DMA Base & Current Address
Channel 5 DMA Base & Current Count
Channel 6 DMA Base & Current Address
Channel 6 DMA Base & Current Count
Channel 7 DMA Base & Current Address
Channel 7 DMA Base & Current Count
Channel 4–7 DMA Command
Channel 4–7 DMA Status
Channel 4–7 DMA Write Single Mask
Channel 4–7 DMA Channel Mode
Channel 4–7 DMA Clear Byte Pointer
Channel 4–7 DMA Master Clear
Channel 4–7 DMA Clear Mask
Channel 4–7 DMA Write All Mask
Default Type
Undefined R/W
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
Undefined
Undefined
R/W
R/W
Undefined
Undefined
Undefined
R/W
R/W
R/W
Undefined
Undefined
R/W
R/W
Undefined
Undefined
Undefined
R/W
WO
RO
000001XXb WO
000000XXb WO
Undefined WO
Undefined WO
Undefined WO
0Fh
R/W
13.2.1
DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0 = 00h; Ch. #1 = 02hAttribute:R/W
Ch. #2 = 04h; Ch. #3 = 06hSize:16 bit (per channel),
Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit
Ch. #7 = CCh;
quantities
Undef
No
Power Well:Core
Datasheet
375