82NM10 Datasheet, PDF (469/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15 SATA Controller Registers
(D31:F2)
15.1 PCI Configuration Registers (SATA–D31:F2)
Note:
Address locations that are not shown should be treated as Reserved.
All of the SATA registers are in the core well. None of the registers can be locked.
Table 15-135.SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 1 of 2)
Offset Mnemonic
Register Name
Default
Type
00h–01h
02h–03h
VID
DID
Vendor Identification
Device Identification
04h–05h
06h–07h
08h
PCICMD
PCISTS
RID
PCI Command
PCI Status
Revision Identification
09h
PI
Programming Interface
0Ah
SCC
Sub Class Code
0Bh
0Dh
10h–13h
14h–17h
18h–1Bh
1Ch–1Fh
20h–23h
24h–27h
BCC
PMLT
PCMD_BAR
PCNL_BAR
SCMD_BAR
SCNL_BAR
BAR
ABAR
Base Class Code
Primary Master Latency Timer
Primary Command Block Base Address
Primary Control Block Base Address
Secondary Command Block Base
Address
Secondary Control Block Base Address
Legacy Bus Master Base Address
AHCI Base Address
2Ch–2Dh
2Eh–2Fh
34h
3Ch
3Dh
SVID
SID
CAP
INT_LN
INT_PN
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
Interrupt Line
Interrupt Pin
8086h
See register
description.
0000h
02B0h
See register
description.
See register
description.
See register
description
01h
00h
00000001h
00000001h
00000001h
RO
RO
R/W, RO
R/WC, RO
RO
See
register
description
See
register
description
RO
RO
R/W, RO
R/W, RO
R/W, RO
00000001h
00000001h
00000000h
0000h
0000h
80h
00h
See register
description.
R/W, RO
R/W, RO
See
register
description
R/WO
R/WO
RO
R/W
RO
Datasheet
469