82NM10 Datasheet, PDF (515/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
31:16
Diagnostics (DIAG) — R/WC. Contains diagnostic error information for use by diagnostic software in
validating correct operation or isolating failure modes:
Bits Description
31:27Reserved
26 Exchanged (X): When set to one this bit indicates a COMINIT signal was received. This bit is
reflected in the interrupt register PxIS.PCS.
25 Unrecognized FIS Type (F): Indicates that one or more FISs were received by the Transport layer
with good CRC, but had a type field that was not recognized.
24 Transport state transition error (T): Indicates that an error has occurred in the transition from
one state to another within the Transport layer since the last time this bit was cleared.
23 Link Sequence Error (S): Indicates that one or more Link state machine error conditions was
encountered. The Link Layer state machine defines the conditions under which the link layer
detects an erroneous transition.
22 Handshake Error (H): Indicates that one or more R_ERR handshake response was received in
response to frame transmission. Such errors may be the result of a CRC error detected by the
recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative
handshake on a transmitted frame.
21 CRC Error (C): Indicates that one or more CRC errors occurred with the Link Layer.
20 Disparity Error (D): This field is not used by AHCI.
19 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding errors occurred.
18 Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy.
17 Phy Internal Error (I): Indicates that the Phy detected some internal error.
16 PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy signal changed state
since the last time this bit was cleared. In the Chipset, this bit will be set when PhyRdy changes
from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the PxIS.PRCS interrupt status
bit and an interrupt will be generated if enabled. Software clears this bit by writing a 1 to it.
15:0
Error (ERR) — R/WC. The ERR field contains error information for use by host software in determining
the appropriate response to the error condition.
If one or more of bits 11:8 of this register are set, the controller will stop the current transfer.
Bits Description
15:12Reserved
11 Internal Error (E): The SATA controller failed due to a master or target abort when attempting to
access system memory.
10 Protocol Error (P): A violation of the Serial ATA protocol was detected. Note: The Chipset does not
set this bit for all protocol violations that may occur on the SATA link.
9 Persistent Communication or Data Integrity Error (C): A communication error that was not recovered
occurred that is expected to be persistent. Persistent communications errors may arise from
faulty interconnect with the device, from a device that has been removed or has failed, or a
number of other causes.
8 Transient Data Integrity Error (T): A data integrity error occurred that was not recovered by the
interface.
7:2 Reserved
1 Recovered Communications Error (M): Communications between the device and host was
temporarily lost but was re-established. This can arise from a device temporarily being removed,
from a temporary loss of Phy synchronization, or from other causes and may be derived from the
PhyNRdy signal between the Phy and Link layers.
0 Recovered Data Integrity Error (I): A data integrity error occurred that was recovered by the
interface through a retry operation or other recovery action.
Datasheet
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