82NM10 Datasheet, PDF (481/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
1:0 Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the
minimum number of PCI clocks between the last IORDY sample point and the IOR#/
IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE
timing register for primary is set.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
15.1.23 SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F2)
Address Offset: 48h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Note:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
Bit
Description
7:4 Reserved
3 Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for secondary channel drive 1
2 Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for secondary drive 0.
1 Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 1
0 Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 0
15.1.24 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2)
Address Offset: 4Ah–4Bh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Note:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation, unless otherwise noted.
Datasheet
481