82NM10 Datasheet, PDF (478/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.17 SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh–2Fh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
Bit
Description
15:0 Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
15.1.18 CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer
offset is 80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits
1:0) in configuration space indicates that the SATA function and PATA functions are
combined (values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is
configure as IDE mode (value of 01).
15.1.19 INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Interrupt Line — R/W. This field is used to communicate to software the interrupt line
that the interrupt pin is connected to.
15.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh
Attribute:
Default Value: See Register Description Size:
RO
8 bits
Bit
Description
7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config
Registers:Offset 3100h:
bits 11:8).
15.1.21 IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2)
Address Offset: Primary: 40h–41h
Secondary: 42h–43h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
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