82NM10 Datasheet, PDF (201/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
The combined data payload must not exceed 32 bytes. The byte length restrictions of
this process call are summarized as follows:
• M ≥ 1 byte
• N ≥ 1 byte
• M + N ≤ 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total
message beginning with the first slave address and using the normal PEC
computational rules. It is highly recommended that a PEC byte be used with the Block
Write-Block Read Process Call. Software must do a read to the command register
(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.
Note that there is no STOP condition before the repeated START condition, and that a
NACK signifies the end of the read transfer.
E32B bit in the Auxiliary Control register must be set when using this protocol.
See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0
for the format of the protocol.
5.20.2
Note:
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. Chipset continuously monitors the
SMBDATA line. When Chipset is attempting to drive the bus to a 1 by letting go of the
SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus
and Chipset will stop transferring data.
If Chipset sees that it has lost arbitration, the condition is called a collision. Chipset will
set the BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt
or SMI#. The processor is responsible for restarting the transaction.
When Chipset is a SMBus master, it drives the clock. When Chipset is sending address
or command as an SMBus master, or data bytes as a master on writes, it drives data
relative to the clock it is also driving. It will not start toggling the clock until the start or
stop condition meets proper setup and hold time. Chipset will also provide minimum
time between SMBus transactions as a master.
Chipset supports the same arbitration protocol for both the SMBus and the System
Management (SMLINK) interfaces.
Datasheet
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