82NM10 Datasheet, PDF (662/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

High Precision Event Timer Registers
Bit
13:9
8
7
6
5
4
3
2
Description
Interrupt Rout (TIMERn_INT_ROUT_CNF) — R/W. This 5-bit field indicates the routing for the
interrupt to the I/O (x) APIC. Software writes to this field to select which interrupt in the I/O (x) will
be used for this timer’s interrupt. If the value is not supported by this particular timer, then the value
read back will not match what is written. The software must only write valid values.
NOTES:
1.
If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a different routing,
and this bit field has no effect for those two timers.
2.
Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21, 22, or 23)
for this field. The Chipset logic does not check the validity of the value written.
3.
Timer 2: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or
23) for this field. The Chipset logic does not check the validity of the value written.
Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set this bit to force a
64-bit timer to behave as a 32-bit timer. This is typically needed if software is not willing to halt the
main counter to read or write a particular timer, and the software is not capable of atomic 64-bit
operations to the timer. This bit is only relevant if the timer is operating in 64-bit mode in which case
that timer can be forced to 32-bit mode by setting this bit. When Timer 0 is switched to 32-bit mode,
the upper 32-bits are loaded with 0’s which will remain when the timer is switched back to 64-bit
mode. If the timer is not in 64-bit mode, then this bit will always be read as 0 and writes will have no
effect.
Timer 0:Bit is read/write (default to 0). 0 = 64 bit; 1= 32 bit
Timers 1, 2:Hardwired to 0. Writes have no effect since these timers are 32-bit only.
Reserved. This bit returns 0 when read.
Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only for Timer 0 if it
has been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly set
the timer’s accumulator. Software does not have to write this bit back to 1 (it automatically clears).
Software should not write a 1 to this bit position if the timer is set to non-periodic mode.
NOTE: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to
periodic mode. Writes will have no effect for Timers 1 and 2.
Timer n Size (TIMERn_SIZE_CAP) — RO. This read only field indicates the size of the timer.
Timer 0:Value is 1 (64-bits).
Timers 1, 2:Value is 0 (32-bits).
Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the hardware
supports a periodic mode for this timer’s interrupt.
Timer 0: Hardwired to 1 (supports the periodic interrupt).
Timers 1, 2: Hardwired to 0 (does not support periodic interrupt).
Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.
Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to
generate a periodic interrupt.
Timers 1, 2: Hardwired to 0. Writes have no effect.
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set to enable timer
n to cause an interrupt when it times out.
0 = Enable.
1 = Disable (Default). The timer can still count and generate appropriate status bits, but will not
cause an interrupt.
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Datasheet