82NM10 Datasheet, PDF (65/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Pin States
3.2
1.
The pull-down resistors on HDA_BIT_CLK (AC ‘97) and HDA_RST# are enabled when
either:
- The LSO bit (bit 3) in the AC’97 Global Control Register (D30:F2:2C) is set to 1, or
- Both Function 2 and Function 3 of Device 30 are disabled.
- Otherwise, the integrated Pull-down resistor is disabled.
2.
The Intel High Definition Audio Link signals must be configured to be an Intel High
Definition Audio Link.
3.
Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ.
4.
Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.
5.
Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.
6.
The pull-down on this signal (in Intel High Definition Audio mode) is only enabled when in
S3_COLD.
7.
Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ.
8.
The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.
9.
Simulation data shows that these resistor values can range from 15 kΩ to 35 kΩ.
10. The pull-down on this signal is only enabled when LAN_RST# is asserted.
11. The internal pull-up is enabled only when the PCIRST# pin is driven low and the PWROK
indication is high.
12. Internal pull-up is enabled during RSMRST# and is disabled within 100 ms after RSMRST#
de-asserts.
13. Simulation data shows that these resistor values can range from 45 kΩ to 170 kΩ.
14. Simulation data shows that these resistor values can range from 15 kΩ to 30 kΩ.
15. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The
internal pull-up is only enabled only during PLTRST# assertion.
16. Simulation data shows that these resistor values can range from 10 kΩ to 30 kΩ.
17. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ.
18. The internal pull-up is enabled only when PCIRST# is low.
Output and I/O Signals Planes and States
Table 3-26 shows the power plane associated with the output and I/O signals, as well
as the state at various times. Within the table, the following terms are used:
“High-Z”
“High”
“Low”
“Defined”
“Undefined”
“Running”
“Off”
Tri-state. the chipset not driving the signal high or low.
The chipset is driving the signal to a logic 1
The chipset is driving the signal to a logic 0
Driven to a level that is defined by the function (will be high or low)
The chipset is driving the signal, but the value is indeterminate.
Clock is toggling or signal is transitioning because function not
stopping
The power plane is off, so the chipset is not driving
Note that the signal levels are the same in S4 and S5, except as noted.
The chipset suspend well signal states are indeterminate and undefined and may glitch,
including input signals acting as outputs, prior to RSMRSTB deassertion. This does not
apply to LAN_RST#, SLP_S3#, SLP_S4#, and SLP_S5#. These signals are determinate
and defined prior to RSMRST# deassertion.
Datasheet
65