82NM10 Datasheet, PDF (231/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Electrical Characteristics
2.
The SERR#, PIRQ[H:A], GPIO11, SMBDATA, SMBCLK, LINKALERT#, and SMLINK[1:0]
signal has an open drain driver and SATALED# has an open collector driver, and the V_OH
spec does not apply. This signal must have an external pull-up resistor.
3.
PCI Express mVdiff p-p = |PETp[x] – PETn[x]|
4.
Applicable only when SATA port signaling rate is 1.5 Gb/s: SATA Vdiff, TX (V_OMAX/MIN8) is
measured at the SATA connector on the transmit side closest to Chipset (generally, the
motherboard connector), where SATA mV diff p-p = |SATAxTXP – SATAxTXN|.
5.
Applicable only when SATA port signaling rate is 3 Gb/s: SATA Vdiff, TX (_VOMAX/MIN8) is
measured at the SATA connector on the transmit side closest to Chipset (generally, the
motherboard connector), where SATA mV diff p-p = |SATAxTXP – SATAxTXN|.
Table 8-96.Other DC Characteristics
Symbol
Parameter
V5REF
Vcc3_3
Vcc1_5,
VccUSBPLL,
VccSATAPLL,
VccDMIPLL
V_CPU_IO
V5REF_Sus
VccSus3_3
Vcc1_05
VccRTC
VDI
VCM
VCRS
VSE
ILI1
ILI2
ILI3
ILI4
CIN
COUT
CI/O
Chipset Core Well Reference
Voltage
I/O Buffer Voltage
Internal Logic and I/O Buffer
Voltage
Processor Interface
Suspend Well Reference
Voltage
Suspend Well I/O Buffer
Voltage
Internal Logic Voltage
Battery Voltage
Differential Input Sensitivity
Differential Common Mode
Range
Output Signal Crossover
Voltage
Single Ended Rcvr Threshold
ATA Input Leakage Current
PCI_3V Hi-Z State Data Line
Leakage
PCI_5V Hi-Z State Data Line
Leakage
Input Leakage Current –
Clock signals
Input Capacitance – All
Other
Output Capacitance
I/O Capacitance
Min
4.75
3.135
1.425
0.945
4.75
3.135
0.998
2.0
0.2
0.8
1.3
0.8
–200
–10
–70
–100
Max
5.25
Unit
V
3.465 V
1.575 V
Notes
1
1
1
1.25 V
1, 2
5.25 V
1
3.465 V
1
1.102 V
1
3.6
V
1
V |(USBPx+,USBPx-)|
2.5
V
Includes VDI
2.0
V
2.0
V
200 µA (0 V < VIN < 5 V)
10
µA (0 V < VIN < 3.3 V)
70
+100
µA Max VIN = 2.7 V Min
VIN = 0.5 V
µA
1
12
pF
FC = 1 MHz
12
pF
12
pF
FC = 1 MHz
FC = 1 MHz
Datasheet
231