82NM10 Datasheet, PDF (664/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Serial Peripheral Interface (SPI)
21 Serial Peripheral Interface
(SPI)
Note:
The Serial Peripheral Interface resides in memory mapped space. This function contains
registers that allow for the setup and programming of devices that reside on the SPI
interface.
All registers in this function (including memory-mapped registers) must be addressable
in Byte, Word, and DWord quantities. The software must always make register accesses
on natural boundaries (i.e., DWord accesses must be on DWord boundaries; word
accesses on word boundaries, etc.) In addition, the memory-mapped register space
must not be accessed with the LOCK semantic exclusive-access mechanism. If software
attempts exclusive-access mechanisms to the SPI memory-mapped space, the results
are undefined.
21.1
Serial Peripheral Interface Memory Mapped
Configuration Registers
The SPI Host Interface registers are memory-mapped in the RCRB Chipset Register
Space with a base address (SPIBAR) of 3020h and are located within the range of
3020h to 308Fh. The individual registers are then accessible at SPIBAR + Offset as
indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Table 21-150.Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 1 of 2)
SPIBAR +
Offset
00h–01h
Mnemonic
SPIS
Register Name
SPI Status
02h–03h
04h–07h
08h–0Fh
SPIC
SPIA
SPID0
SPI Control
SPI Address
SPI Data 0
10h–17h
SPID1
SPI Data 1
18h–1Fh
SPID2
SPI Data 2
20h–27h
SPID3
SPI Data 3
28h–2Fh
SPID4
SPI Data 4
30h–37h
SPID5
SPI Data 5
Default
Access
See Register
Description
0001h
00000000h
See Register
Description
00000000
00000000h
00000000
00000000h
00000000
00000000h
00000000
00000000h
00000000
00000000h
RO, R/WC,
R/WLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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