82NM10 Datasheet, PDF (301/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.3
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address: 04h–05h
Default Value: 0000h
Attribute:
Size:
RO, R/W
16 bits
Bit
Description
15:11 Reserved
10 Interrupt Disable — R/W.
0 = Enable.
1 = Disables LAN controller to assert its INTA signal.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN controller
will not run fast back-to-back PCI cycles.
8 SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable. Allow SERR# to be asserted.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented.
6 Parity Error Response (PER) — R/W.
0 = The LAN controller will ignore PCI parity errors.
1 = The integrated LAN controller will take normal action when a PCI parity error is
detected and will enable generation of parity on DMI.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented.
4 Memory Write and Invalidate Enable (MWIE) — R/W.
0 = Disable. The LAN controller will not use the Memory Write and Invalidate command.
1 = Enable.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN controller ignores special
cycles.
2 Bus Master Enable (BME) — R/W.
0 = Disable.
1 = Enable. The Chipset's integrated LAN controller may function as a PCI bus master.
1 Memory Space Enable (MSE) — R/W.
0 = Disable.
1 = Enable. The Chipset's integrated LAN controller will respond to the memory space
accesses.
0 I/O Space Enable (IOSE) — R/W.
0 = Disable.
1 = Enable. The Chipset's integrated LAN controller will respond to the I/O space
accesses.
Datasheet
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