82NM10 Datasheet, PDF (15/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

15.2
15.1.10PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2) ....................................................................... 476
15.1.11PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2).................................................................................... 476
15.1.12SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) .......................................................................... 477
15.1.13SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1) .......................................................................... 477
15.1.14BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2).................................................................................... 477
15.1.15ABAR — AHCI Base Address Register
(SATA–D31:F2).................................................................................... 478
15.1.16SVID—Subsystem Vendor Identification Register
(SATA–D31:F2).................................................................................... 479
15.1.17SID—Subsystem Identification Register (SATA–D31:F2) ............................ 479
15.1.18CAP—Capabilities Pointer Register (SATA–D31:F2).................................... 479
15.1.19INT_LN—Interrupt Line Register (SATA–D31:F2) ...................................... 479
15.1.20INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................ 480
15.1.21IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2) ......................... 480
15.1.22IDE_TIMS — Slave IDE Timing Register (SATA–D31:F2) ............................ 481
15.1.23SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F2).................................................................................... 482
15.1.24SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2).................................................................................... 483
15.1.25IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F2).................................................................................... 485
15.1.26PID—PCI Power Management Capability Identification
Register (SATA–D31:F2) ....................................................................... 486
15.1.27PC—PCI Power Management Capabilities Register
(SATA–D31:F2).................................................................................... 486
15.1.28PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2) ....................................................................... 487
15.1.29MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 487
15.1.30MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2)......... 488
15.1.31MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2)....... 489
15.1.32MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............ 489
15.1.33MAP—Address Map Register (SATA–D31:F2) ............................................ 489
15.1.34PCS—Port Control and Status Register (SATA–D31:F2).............................. 490
15.1.35SIR—SATA Initialization Register ............................................................ 491
15.1.36SIRI—SATA Indexed Registers Index ...................................................... 492
15.1.37STRD—SATA Indexed Register Data ........................................................ 492
15.1.38SCAP0—SATA Capability Register 0 (SATA–D31:F2) .................................. 493
15.1.39SCAP1—SATA Capability Register 1 (SATA–D31:F2) .................................. 494
15.1.40ATC—APM Trapping Control Register (SATA–D31:F2) ................................ 495
15.1.41ATS—APM Trapping Status Register (SATA–D31:F2) ................................. 495
15.1.42SP — Scratch Pad Register (SATA–D31:F2) .............................................. 495
15.1.43BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................... 496
15.1.44BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................ 497
15.1.45BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................ 497
Bus Master IDE I/O Registers (D31:F2) .............................................................. 497
15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 498
15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ............................... 499
15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2) ................................................................................ 500
Datasheet
15