82NM10 Datasheet, PDF (440/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.9.5
TCO2_STS—TCO2 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +06h
0000h
No
Attribute:
Size:
Power Well:
R/W, R/WC
16-bit
Resume
(Except Bit 0, in RTC)
Bit
Description
15:5
4
3
2
1
0
Reserved
SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to
go directly into pre-determined sleep state. This avoids race conditions. Software clears
this bit by writing a 1 to it.
0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit
from S3–S5 states.
1 = Chipset sets this bit to 1 when it receives the SMI message on the SMLink's Slave
Interface.
Reserved
BOOT_STS — R/WC.
0 = Cleared by Chipset based on RSMRST# or by software writing a 1 to this bit. Note
that software should first clear the SECOND_TO_STS bit before writing a 1 to clear
the BOOT_STS bit.
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not
fetched the first instruction.
If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the
Chipset will reboot using the ‘safe’ multiplier (1111). This allows the system to recover
from a processor frequency multiplier that is too high, and allows the BIOS to check the
BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the
BIOS knows that the processor has been programmed to an invalid multiplier.
SECOND_TO_STS — R/WC.
0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.
1 = Chipset sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently)
set and a second timeout occurred before the TCO_RLD register was written. If this
bit is set and the NO_REBOOT config bit is 0, then the Chipset will reboot the
system after the second timeout. The reboot is done by asserting PLTRST#.
Intruder Detect (INTRD_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.
1 = Set by Chipset to indicate that an intrusion was detected. This bit is set even if the
system is in G3 state.
NOTE: This bit has a recovery time. After writing a 1 to this bit position (to clear it), the
bit may be read back as a 1 for up 65 microseconds before it is read as a 0.
Software must be aware of this recovery time when reading this bit after
clearing it.
NOTE: If the INTRUDER# signal is active when the software attempts to clear the
INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again
immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah,
bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes
inactive and then active again, there will not be further SMI’s (because the
INTRD_SEL bits would select that no SMI# be generated).
NOTE: If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is
written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input
signal goes inactive. Note that this is slightly different than a classic sticky bit,
since most sticky bits would remain active indefinitely when the signal goes
active and would immediately go inactive when a 1 is written to the bit.
440
Datasheet