82NM10 Datasheet, PDF (84/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.2.4.3
5.2.4.4
will result in a command complete interrupt. The only exception to this rule is a write to
disable the command complete interrupt which will not result in a command complete
interrupt.
A single write to the Slot Control register is considered to be a single command, and
hence receives a single command complete, even if the write affects more than one
field in the Slot Control Register.
Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user.
This attention button press will result in a the PCI Express message
“Attention_Button_Pressed” from the device. Upon receiving this message, the root
port will set SLSTS.ABP (D28:F0/F1/F2/F3:Offset 5Ah:bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/
F3:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The
interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a
new interrupt will not be generated.
SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To
support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be
routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3:Offset D8h:bit
30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS (D28:F0/
F1/F2/F3:Offset DCh:bit 30) to be set.
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME
(D28:F0/F1/F2/F3:Offset D8h:bit 1). When this bit is set, Hot-Plug events can cause
SMI status bits in SMSCS to be set. Supported Hot-Plug events and their corresponding
SMSCS bit are:
• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3:Offset DCh:bit 3)
• Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3:Offset DCh:bit 1)
• Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3:Offset DCh:bit 2)
• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3:Offset DCh:bit 4)
When any of these bits are set, SMI # will be generated. These bits are set regardless
of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur
concurrently with an interrupt or SCI.
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Datasheet