82NM10 Datasheet, PDF (68/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Pin States
Table 3-26.Power Plane and States for Output and I/O Signals (Sheet 3 of 4)
Signal Name
Power
Plane
During
PLTRST#⁶ /
RSMRST#⁷
Immediately
after
PLTRST#⁶ /
RSMRST#⁷
C3/C4
S1
S3_COLD13
S4/
S5
A20M#
CPUPWRGD /
GPIO49
IGNNE#
INIT#
INIT3_3V#
INTR
NMI
SMI#
STPCLK#
DPSLP#
SMBCLK,
SMBDATA
Processor Interface
Core
Dependant on See Note 8
Defined High
Off
Off
A20GATE
Signal
Core
See Note 3
High
High
High
Off
Off
Core
Core
Core
Core
Core
Core
Core
Core
Suspend
High
High
High
See Note 8
See Note 8
High
High
High
See Note 8
High
High
See Note 8
See Note 8
High
High
High
SMBus Interface
High-Z
High-Z
High
High
High
Defined
Defined
Defined
Low
High/
Low
High
High
High
Low
Low
High
Low
High
Defined Defined
System Management Interface
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Off
Off
Off
Off
Off
Off
Off
Off
Define
d
SMLINK[1:0]
LINKALERT#
Suspend
Suspend
High-Z
High-Z
Defined Defined
High-Z
High-Z
Defined Defined
Miscellaneous Signals
Defined
Defined
Define
d
Define
d
SPKR
HDA_RST#
HDA_SDOUT
HDA_SYNC
HDA_BIT_CLK
Core
Suspend
Core
Core
Core
High-Z with
Internal Pull-
down
Low
Defined Defined
Intel HD Audio Interface
Low
Low¹¹
High
High-Z with
Internal Pull-
down
Running
Running
High-Z with
Internal Pull-
down
High-Z with
Internal Pull-
down
Running
Low¹¹
Running
Running
TBD
Low
Low
Low
Off
Low
Off
Off
Off
Off
Low
Off
Off
Off
68
Datasheet