82NM10 Datasheet, PDF (119/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.9.4.10
Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest
ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of
the PIC within Chipset, as the interrupt being serviced currently is the interrupt entered
with the interrupt acknowledge. When the PIC is operated in modes that preserve the
fully nested structure, software can determine which ISR bit to clear by issuing a
Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is
in the special mask mode. An EOI command must be issued for both the master and
slave controller.
Automatic End of Interrupt Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller and not
the slave controller.
5.9.5
5.9.5.1
5.9.5.2
Masking Interrupts
Masking on an Individual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller masks all requests for service
from the slave controller.
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The special mask mode enables all interrupts not masked by a bit set in the Mask
register. Normally, when an interrupt service routine acknowledges an interrupt without
issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority
requests. In the special mask mode, any interrupts may be selectively enabled by
loading the Mask Register with the appropriate pattern. The special mask mode is set
by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
5.9.6
Steering PCI Interrupts
Chipset can be programmed to allow PIRQA#-PIRQH# to be internally routed to
interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the through
the PIRQx Route Control registers, located at 60–63h and 68–6Bh in Device
31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If
interrupt steering is not required, the Route registers can be programmed to disable
steering.
Datasheet
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