82NM10 Datasheet, PDF (296/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
Bit
17
16
15
14
13:12
11
10
9
8
7
6:5
4
3
Description
PCI Express 2 Disable (PE2D) — R/W. When disabled, the link for this port is put
into the link down state.
0 = PCI Express port #2 is enabled. (Default)
1 = PCI Express port #2 is disabled
PCI Express 1 Disable (PE1D) — R/W. When disabled, the link for this port is put
into the link down state.
0 = PCI Express port #1 is enabled. (Default)
1 = PCI Express port #1 is disabled.
EHCI Disable (EHCID) — R/W.
0 = The EHCI is enabled. (Default)
1 = The EHCI is disabled.
LPC Bridge Disable (LBD) — R/W.
0 = The LPC bridge is enabled. (Default)
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following
additional spaces will no longer be decoded by the LPC bridge:
• Memory cycles below 16 MB (1000000h)
• I/O cycles below 64 KB (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is
set, but the aliases at the top of 1 MB (the E and F segment) no longer will be
decoded.
Reserved
UHCI #4 Disable (U4D) — R/W.
0 = The 4th UHCI (ports 6 and 7) is enabled. (Default)
1 = The 4th UHCI (ports 6 and 7) is disabled.
UHCI #3 Disable (U3D) — R/W.
0 = The 3rd UHCI (ports 4 and 5) is enabled. (Default)
1 = The 3rd UHCI (ports 4 and 5) is disabled.
UHCI #2 Disable (U2D) — R/W.
0 = The 2nd UHCI (ports 2 and 3) is enabled. (Default)
1 = The 2nd UHCI (ports 2 and 3) is disabled.
UHCI #1 Disable (U1D) — R/W.
0 = The 1st UHCI (ports 0 and 1) is enabled. (Default)
1 = The 1st UHCI (ports 0 and 1) is disabled.
Hide Internal LAN (HIL) — R/W.
0 = The LAN controller is enabled. (Default)
1 = The LAN controller is disabled and will not decode configuration cycles off of P
Reserved
Intel HD Audio Disable (ZD) — R/W.
0 = The Intel High Definition Audio controller is enabled. (Default)
1 = The Intel High Definition Audio controller is disabled and its PCI configuration
space is not accessible.
SM Bus Disable (SD) — R/W.
0 = The SM Bus controller is enabled. (Default)
1 = The SM Bus controller is disabled. In Chipset and previous, this also disabled the
I/O space. In the Chipset, it only disables the configuration space.
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Datasheet