82NM10 Datasheet, PDF (454/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
Bit
Description
6:0 Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout.
14.1.11 BASE—Base Address Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
20h–23hAttribute:R/W, RO
Default Value:
00000001hSize:32 bits
Bit
Description
31:16 Reserved
15:5 Base Address — R/W. Bits [15:5] correspond to I/O address signals AD [15:5],
respectively. This gives 32 bytes of relocatable I/O space.
4:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate that the base address
field in this register maps to I/O space.
14.1.12 SVID — Subsystem Vendor Identification Register
(USB—D29:F0/F1/F2/F3)
Address Offset: 2Ch–2Dh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
Bit
Description
15:0
Subsystem Vendor ID (SVID) — R/WO. BIOS sets the value in this register to identify
the Subsystem Vendor ID. The USB_SVID register, in combination with the USB
Subsystem ID register, enables the operating system to distinguish each subsystem
from the others.
NOTE: The software can write to this register only once per core well reset. Writes
should be done as a single, 16-bit cycle.
14.1.13 SID — Subsystem Identification Register
(USB—D29:F0/F1/F2/F3)
Address Offset: 2Eh–2Fh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
Bit
Description
15:0
Subsystem ID (SID) — R/WO. BIOS sets the value in this register to identify the
Subsystem ID. The SID register, in combination with the SVID register (D29:F0/F1/F2/
F3:2C), enables the operating system to distinguish each subsystem from other(s). The
value read in this register is the same as what was written to the IDE_SID register.
NOTE: The software can write to this register only once per core well reset. Writes
should be done as a single, 16-bit cycle.
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Datasheet