82NM10 Datasheet, PDF (268/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.3
10.1.4
10.1.5
10.1.6
VCAP2—Virtual Channel Capability #2 Register
Offset Address: 0008–000Bh
Default Value: 00000001h
Attribute:
Size:
RO
32-bit
Bit
Description
31:24
23:8
7:0
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is
present for VC arbitration since it is fixed.
Reserved
VC Arbitration Capability (AC) — RO. This field indicates that the VC arbitration is
fixed in the root complex. VC1 is highest priority and VC0 is lowest priority.
PVC—Port Virtual Channel Control Register
Offset Address: 000C–000Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16-bit
Bit
Description
15:04
3:1
0
Reserved
VC Arbitration Select (AS) — RO. This field indicates which VC should be
programmed in the VC arbitration table. The root complex takes no action on the
setting of this field since there is no arbitration table.
Load VC Arbitration Table (LAT) — RO. This bit indicates that the table
programmed should be loaded into the VC arbitration table. This bit is defined as
read/write with always returning 0 on reads.
PVS—Port Virtual Channel Status Register
Offset Address: 000E–000Fh
Default Value: 0000h
Attribute:
Size:
RO
16-bit
Bit
Description
15:01
0
Reserved
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status
of the VC Arbitration table when it is being updated. This field is always 0 in the root
complex since there is no VC arbitration table.
V0CAP—Virtual Channel 0 Resource Capability Register
Offset Address: 0010–0013h
Default Value: 00000001h
Attribute:
Size:
RO
32-bit
Bit
Description
31:24
23
22:16
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration
table since the arbitration is fixed.
Reserved
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and
therefore this field is not used.
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Datasheet