82NM10 Datasheet, PDF (313/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
Bit
1:0 Reserved
Description
11.2.2
SCB_CMD—System Control Block Command Word
Register (LAN Controller—B1:D8:F0)
Offset Address: 02h–03h
Default Value: 0000h
Attribute:
Size:
R/W, WO
16 bits
The processor places commands for the Command and Receive units in this register.
Interrupts are also acknowledged in this register.
Bit
Description
15 CX Mask (CX_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of a CX interrupt.
14 FR Mask (FR_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an FR interrupt.
13 CNA Mask (CNA_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of a CNA interrupt.
12 RNR Mask (RNR_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an RNR interrupt.
11 ER Mask (ER_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an ER interrupt.
10 FCP Mask (FCP_MSK) — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an FCP interrupt.
9 Software Generated Interrupt (SI) — WO.
0 = No Effect.
1 = Setting this bit causes the LAN controller to generate an interrupt.
8 Interrupt Mask (IM) — R/W. This bit enables or disables the LAN controller’s
assertion of the INTA# signal. This bit has higher precedence that the Specific Interrupt
Mask bits and the SI bit.
0 = Enable the assertion of INTA#.
1 = Disable the assertion of INTA#.
Datasheet
313