82NM10 Datasheet, PDF (185/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.19.6.1
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
• The Host System Error status bit is set
• The DMA engines are halted after completing up to one more transaction on the
USB interface
• If enabled (by the Host System Error Enable), then an interrupt is generated
• If the status is Master Abort, then the Received Master Abort bit in configuration
space is set
• If the status is Target Abort, then the Received Target Abort bit in configuration
space is set
• If enabled (by the SERR Enable bit in the function’s configuration space), then the
Signaled System Error bit in configuration bit is set.
5.19.7
5.19.7.1
5.19.7.2
USB 2.0 Power Management
Pause Feature
This feature allows platforms (especially Netbook systems) to dynamically enter low-
power states during brief periods when the system is idle (i.e., between keystrokes).
This is useful for enabling power management features like Intel SpeedStep technology
in Chipset Netbook Only. The policies for entering these states typically are based on
the recent history of system bus activity to incrementally enter deeper power
management states. Normally, when the EHC is enabled, it regularly accesses main
memory while traversing the DMA schedules looking for work to do; this activity is
viewed by the power management software as a non-idle system, thus preventing the
power managed states to be entered. Suspending all of the enabled ports can prevent
the memory accesses from occurring, but there is an inherent latency overhead with
entering and exiting the suspended state on the USB ports that makes this
unacceptable for the purpose of dynamic power management. As a result, the EHCI
software drivers are allowed to pause the EHC’s DMA engines when it knows that the
traffic patterns of the attached devices can afford the delay. The pause only prevents
the EHC from generating memory accesses; the SOF packets continue to be generated
on the USB ports (unlike the suspended state).
Suspend Feature
The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,
Section 4.3 describes the details of Port Suspend and Resume.
Datasheet
185