82NM10 Datasheet, PDF (587/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.1.36 PVCCAP2 — Port VC Capability Register 2
(Intel HD Audio Controller—D27:F0)
Address Offset: 108h–10Bh
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration
table is not present.
23:8 Reserved.
7:0 VC Arbitration Capability — RO. Hardwired to 0. These bits are not applicable since
the Intel HD Audio controller reports a 0 in the Low Priority Extended VC Count bits in
the PVCCAP1 register.
18.1.37 PVCCTL — Port VC Control Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 10Ch–10Dh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:4
3:1
0
Reserved.
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However,
these bits are not applicable since the Intel HD Audio controller reports a 0 in the Low
Priority Extended VC Count bits in the PVCCAP1 register.
Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not
present.
18.1.38 PVCSTS—Port VC Status Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 10Eh-10Fh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:1
0
Reserved.
VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not
present.
Datasheet
587