82NM10 Datasheet, PDF (505/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.3.2.2
15.3.2.3
15.3.2.4
PxCLBU—Port [1:0] Command List Base Address Upper
32-Bits Register (D31:F2)
Address Offset: Port 0: ABAR + 104h
Port 1: ABAR + 184h
Attribute:
R/W
Default Value: Undefined
Size:
32 bits
Bit
Description
31:0
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the command list base address for this port. This base is used when fetching
commands to execute.
Note that these bits are not reset on a HBA reset.
PxFB—Port [1:0] FIS Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 108h
Port 1: ABAR + 188h
Default Value: Undefined
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:8
7:0
FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The
structure pointed to by this address range is 256 bytes in length. This address must be
256-byte aligned, as indicated by bits 31:3 being read/write.
Note that these bits are not reset on a HBA reset.
Reserved — RO
PxFBU—Port [1:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset: Port 0: ABAR + 10Ch
Port 1: ABAR + 18Ch
Attribute:
R/W
Default Value: Undefined
Size:
32 bits
Bit
Description
31:3
2:0
FIS Base Address Upper (FBU) — R/W. Indicates the upper 32-bits for the received
FIS base for this port.
Note that these bits are not reset on a HBA reset.
Reserved
Datasheet
505