82NM10 Datasheet, PDF (630/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.19 CAPP—Capabilities List Pointer Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 34h
Default Value: 40h
Attribute:
Size:
R0
8 bits
Bit
Description
7:0 Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first
entry in the capabilities list is at 40h in configuration space.
19.1.20 INTR—Interrupt Information Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 3Ch–3Dh
Default Value: See bit description
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:8
Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the root
port. At reset, this register takes on the following values that reflect the reset state of
the D28IP register in chipset configuration space:
Port
1
2
3
4
Reset Value
D28IP.P1IP
D28IP.P2IP
D28IP.P3IP
D28IP.P4IP
NOTE: The value that is programmed into D28IP is always reflected in this register.
7:0 Interrupt Line (ILINE) — R/W. Default = 00h. This field is a software written value to
indicate which interrupt line (vector) the interrupt is connected to. No hardware action
is taken on this register.
19.1.21 BCTRL—Bridge Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 3Eh–3Fh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:12
11
10
9
8
7
Reserved
Discard Timer SERR# Enable (DTSE). Reserved per PCI Express* Base
Specification, Revision 1.0a
Discard Timer Status (DTS). Reserved per PCI Express* Base Specification,
Revision 1.0a.
Secondary Discard Timer (SDT). Reserved per PCI Express* Base Specification,
Revision 1.0a.
Primary Discard Timer (PDT). Reserved per PCI Express* Base Specification,
Revision 1.0a.
Fast Back to Back Enable (FBE). Reserved per PCI Express* Base Specification,
Revision 1.0a.
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