82NM10 Datasheet, PDF (24/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

19.1.65ULBA — Upstream Link Base Address Register
(PCI Express—D28:F0/F1/F2/F3) ............................................................ 657
19.1.66PEETM — PCI Express Extended Test Mode Register
(PCI Express—D28:F0/F1/F2/F3) ............................................................ 657
20 High Precision Event Timer Registers..................................................................... 658
20.1
Memory Mapped Registers ................................................................................ 658
20.1.1 GCAP_ID—General Capabilities and Identification Register ......................... 659
20.1.2 GEN_CONF—General Configuration Register ............................................. 660
20.1.3 GINTR_STA—General Interrupt Status Register......................................... 660
20.1.4 MAIN_CNT—Main Counter Value Register ................................................. 661
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register ..................... 661
20.1.6 TIMn_COMP—Timer n Comparator Value Register ..................................... 663
21 Serial Peripheral Interface (SPI).................................................................................. 664
21.1
Serial Peripheral Interface Memory Mapped Configuration Registers........................ 664
21.1.1 SPIS—SPI Status Register
(SPI Memory Mapped Configuration Registers).......................................... 665
21.1.2 SPIC—SPI Control Register
(SPI Memory Mapped Configuration Registers).......................................... 666
21.1.3 SPIA—SPI Address Register
(SPI Memory Mapped Configuration Registers).......................................... 667
21.1.4 SPID[N] —SPI Data N Register
(SPI Memory Mapped Configuration Registers).......................................... 668
21.1.5 BBAR—BIOS Base Address Register
(SPI Memory Mapped Configuration Registers).......................................... 669
21.1.6 PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 669
21.1.7 OPTYPE—Opcode Type Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 670
21.1.8 OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 670
21.1.9 PBR[N]—Protected BIOS Range [N]
(SPI Memory Mapped Configuration Registers).......................................... 671
Figures
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Intel NM10 Family Express Chipset Features Block Diagram..........................31
Interface Signals Block Diagram ...............................................................44
Example External RTC Circuit ...................................................................63
Nettop Only Conceptual System Clock Diagram...........................................75
Netbook Only Conceptual Clock Diagram....................................................75
Generation of SERR# to Platform ..............................................................83
64-Word EEPROM Read Instruction Waveform ............................................91
LPC Interface Diagram.............................................................................98
LPC Bridge SERR# Generation ................................................................ 104
Chipset DMA Controller.......................................................................... 104
DMA Request Assertion through LDRQ# ................................................... 108
Coprocessor Error Timing Diagram .......................................................... 134
SATA Power States ............................................................................... 172
USB Legacy Keyboard Flow Diagram ....................................................... 183
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Datasheet