82NM10 Datasheet, PDF (205/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
Note:
The external microcontroller should not attempt to access chipset’s SMBus slave logic
until either:
• 800 milliseconds after both: RTEST# is high and RSMRST# is high, OR
• the PLTRST# de-asserts
The 800 ms case is based on the scenario where the RTC Battery is dead or missing
such that the RTC Power Well comes up simultaneously with Suspend Well. In this case,
the RTC clock may take a while to stabilize. Chipset uses the RTC clock to extend the
internal RSMRST# by ~100 ms. Therefore, if the clock is slow to toggle, this time could
be extended. 800 ms is assumed to be sufficient guardband for this.
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, Chipset slave logic's behavior is undefined. This is interpreted
as an unexpected idle and should be avoided when performing management activities
to the slave logic.
When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if Chipset slave address (RCV_SLVA) is left at 44h
(default), the external micro controller would use an address of 88h/89h (write/read).
5.20.7.1
Note:
Format of Slave Write Cycle
The external master performs Byte Write commands to Chipset SMBus Slave I/F. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field
(bits 20:27) indicate the value that should be written to that register.
If Chipset is sent a ‘Hard Reset Without Cycling’ command on SMBus while the system
is in S4 or S5, the reset command will not be executed until the next wake event.
SMBus write commands sent after the Hard Reset Without Cycling command and
before the wake event will be NAKed by Chipset. This also applies to any SMBus wake
commands sent after a Hard Reset Without Cycling command, such that the SMBus
wake command will not cause the system to wake. Any SMBus read that is accepted by
Chipset will complete normally.
Table 5-80 has the values associated with the registers.
Table 5-80.Slave Write Registers
Register
Function
0
1–3
4
5
6–7
8
9–FFh
Command Register. See Table 5-81 below for legal values written to this register.
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Reserved
Reserved
Datasheet
205