82NM10 Datasheet, PDF (81/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
Power Management
S3/S4/S5 Support
Software initiates the transition to S3/S4/S5 by performing an IO write to the Power
Management Control register in Chipset. After the IO write completion has been
returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction
Layer Packet) message on it's downstream link. The device attached to the link will
eventually respond with a PME_TO_Ack TLP message followed by sending a
PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.
When all of Chipset root ports links are in the L2/L3 Ready state, Chipset power
management control logic will proceed with the entry into S3/S4/S5.
Prior to entering S3, software is required to put each device into D3_HOT. When a device
is put into D3_HOT, it will initiate entry into a L1 link state by sending a PM_Enter_L1
DLLP. Thus, under normal operating conditions when the root ports sends the
PME_Turn_Off message, the link will be in state L1. However, when the root port is
instructed to send the PME_Turn_Off message, it will send it whether or not the link
was in L1. Endpoints attached to Chipset can make no assumptions about the state of
the link prior to receiving a PME_Turn_Off message.
Resuming from Suspended State
The root port contains enough circuitry in the resume well to detect a wake event thru
the WAKE# signal and to wake the system. When WAKE# is detected asserted, an
internal signal is sent to the power management controller of Chipset to cause the
system to wake up. This internal message is not logged in any register, nor is an
interrupt/GPE generated due to it.
Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a
device requesting service will send a PM_PME message continuously, until acknowledge
by the root port. The root port will take different actions depending upon whether this
is the first PM_PME has been received, or whether a previous message has been
received but not yet serviced by the operating system.
If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3:Offset 60h:bit 16 is
cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID
(D28:F0/F1/F2/F3:Offset 60h:bits 15:0). If an interrupt is enabled via RCTL.PIE
(D28:F0/F1/F2/F3:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can
be either a pin or a MSI if MSI is enabled via MC.MSIE (D28:F0/F1/F2/F3:Offset 82h:bit
0). See Section 5.2.2.4 for SMI/SCI generation.
If this is a subsequent message received (RSTS.PS is already set), the root port will set
RSTS.PP (D28:F0/F1/F2/F3:Offset 60h:bit 17) and log the PME Requester ID from the
message in a hidden register. No other action will be taken.
Datasheet
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