82NM10 Datasheet, PDF (651/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
18
17
16
15
14
13
12
11:5
4
3:1
0
Malformed TLP Status (MT) — R/WC.
0 = Malformed TLP was Not received.
1 = Malformed TLP was received.
Receiver Overflow Status (RO) — R/WC.
0 = Receiver overflow did Not occur.
1 = Receiver overflow occurred.
Unexpected Completion Status (UC) — R/WC.
0 = Unexpected completion was Not received.
1 = Unexpected completion was received.
Completion Abort Status (CA) — R/WC.
0 = Completer abort was Not received.
1 = Completer abort was received.
Completion Timeout Status (CT) — R/WC.
0 = Completion did Not time out.
1 = Completion timed out.
Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not
supported.
Poisoned TLP Status (PT) — R/WC.
0 = Poisoned TLP was Not received.
1 = Poisoned TLP was received.
Reserved
Data Link Protocol Error Status (DLPE) — R/WC.
0 = Data link protocol error did Not occur.
1 = Data link protocol error occurred.
Reserved
Training Error Status (TE) — RO. Training Errors not supported.
19.1.56 UEM — Uncorrectable Error Mask
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 148h–14Bh
Default Value: 00000000h
Attribute:
Size:
R/WO, RO
32 bits
When set, the corresponding error in the UES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
Bit
Description
31:21 Reserved
20 Unsupported Request Error Mask (URE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
19 ECRC Error Mask (EE) — RO. ECRC is not supported.
18 Malformed TLP Mask (MT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Datasheet
651