82NM10 Datasheet, PDF (636/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
1:0 Active State Link PM Control (APMC) — R/W. This bit indicates whether the root
port should enter L0s or L1 or both.
00b
Disabled
01b
L0s Entry is Enabled
10b
L1 Entry is Enabled
11b
L0s and L1 Entry Enabled
19.1.29 LSTS—Link Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 52h–53h
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
Description
15:14 Reserved
13 Data Link Layer Active (DLLA) — RO. D
0 = Data Link Control and Management State Machine is not in the DL_Active state.
(Default)
1 = Data Link Control and Management State Machine is in the DL_Active state.
12 Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Chipset uses the
same reference clock as on the platform and does not generate its own clock.
11 Link Training (LT) — RO.
0 = Link training completed. (Default)
1 = Link training is occurring.
10 Link Training Error (LTE) — RO. Not supported. Set value is 0b.
9:4 Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the
given PCI Express* link. The contents of this NLW field is undefined if the link has not
successfully trained.
Port #
1
2
3
4
Possible Values
000001b, 000010b, 000100b
000001b
000001b
000001b
NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported),
000100 = x4 linkwidth
3:0 Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI
Express* link.
01h = Link is 2.5 Gb/s.
636
Datasheet