82NM10 Datasheet, PDF (241/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Electrical Characteristics
5.
Note that this does not apply for synchronous SMIs.
6.
These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
7.
This is a clock generator specification.
8.
This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert
time for DPRSLPVR has been met, then this is permitted to be 0.
9.
This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert
time for STP_CPU# has been met, then this is permitted to be 0.
10. This value should be at most a few clocks greater than the minimum.
11. This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs
(245.6 µs).
12. Chipset STPCLK# assertion will trigger the processor to send a stop grant acknowledge
cycle. The timing for this cycle getting to Chipset is dependant on the processor and the
memory controller.
13. Chipset has no maximum timing requirement for this transition. It is up to the system
designer to determine if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control
the power planes.
14. t290, t293, and t294 apply during S0 to G3 transitions only. In addition, the timings are
not applied to V5REF. V5REF timings are bonded by power sequencing.
15. A Vcc supply is inactive when the voltage is below the min value specified in Table 8-96.
16. f the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5#
are asserted together similar to timing t287 (PCIRST# active to SLP_S3# active).
17. t303 applies during S0 to S3-S5 transitions.
18. RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.1 V.
8.5
Timing Diagrams
Figure 8-21. Clock Timing
Figure 8-22. Valid Delay from Rising Clock Edge
Clock
1.5V
Output
Valid Delay
VT
Datasheet
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