82NM10 Datasheet, PDF (307/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.16 INT_LN — Interrupt Line Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Interrupt Line (INT_LN) — R/W. This field identifies the system interrupt line to
which the LAN controller’s PCI interrupt request pin (as defined in the Interrupt Pin
Register) is routed.
11.1.17 INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Dh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s
interrupt request is connected to PIRQA#. However, in the Chipset implementation,
when the LAN controller interrupt is generated PIRQE# will go active, not PIRQA#. Note
that if the PIRQE# signal is used as a GPI, the external visibility will be lost (though
PIRQE# will still go active internally).
11.1.18 MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Eh
Default Value: 08h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in
increments of 0.25 μs) that the LAN controller needs to retain ownership of the PCI bus
when it initiates a transaction.
11.1.19 MAX_LAT — Maximum Latency Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Fh
Default Value: 38h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Maximum Latency (MAX_LAT) — RO. This field defines how often (in increments of
0.25 μs) the LAN controller needs to access the PCI bus.
Datasheet
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