82NM10 Datasheet, PDF (557/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.1.6
17.1.7
17.1.8
17.1.9
PI—Programming Interface Register (SMBUS—D31:F3)
Offset Address: 09h
Default Value: 00h
Bit
7:0 Reserved
Attribute:
Size:
Description
RO
8 bits
SCC—Sub Class Code Register (SMBUS—D31:F3)
Address Offset: 0Ah
Default Value: 05h
Bit
7:0 Sub Class Code (SCC) — RO.
05h = SM Bus serial controller
Attributes:
Size:
Description
RO
8 bits
BCC—Base Class Code Register (SMBUS—D31:F3)
Address Offset: 0Bh
Default Value: 0Ch
Bit
7:0 Base Class Code (BCC) — RO.
0Ch = Serial controller.
Attributes:
Size:
Description
RO
8 bits
SMB_BASE—SMBUS Base Address Register
(SMBUS—D31:F3)
Address Offset: 20–23h
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32-bits
Bit
Description
31:16 Reserved — RO
15:5 Base Address — R/W. This field provides the 32-byte system I/O base address for the
Chipset SMB logic.
4:1 Reserved — RO
0 IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.
Datasheet
557