82NM10 Datasheet, PDF (426/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
5
AC97_STS — R/WC. This bit will be set to 1 when the codecs are attempting to
wake the system and the PME events for the codecs are armed for wakeup. A PME is
armed by programming the appropriate PMEE bit in the Power Management Control
and Status register at bit 8 of offset 54h in each AC’97 function.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the codecs are attempting to wake the system. The
AC97_STS bit gets set only from the following case:
1.The PMEE bit for the function is set, and The AC-link bit clock has been shut and
the routed ACZ_SDIN line is high (for audio, if routing is disabled, no wake events
are allowed.
NOTE: This bit is not affected by a hard reset caused by a CF9h write.
4
USB2_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 2 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake
event will be generated if the corresponding USB2_EN bit is set.
3
USB1_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 1 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake
event will be generated if the corresponding USB1_EN bit is set.
2
SWGPE_STS — R/WC.
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
1
HOT_PLUG_STS — R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the
HOT_PLUG_EN bit is set in the GEP0_EN register.
1
Reserved
0
Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0 = THRM# signal Not driven active as defined by the THRM_POL bit
1 = Set by hardware anytime the THRM# signal is driven active as defined by the
THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the
THRM_STS bit will also generate a power management event (SCI or SMI#).
13.8.3.11 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
Attribute:
00000000h
Size:
No
Usage:
Bits 0–7, 9, 12, 14–31 Resume,
Bits 8, 10–11, 13 RTC
R/W
32-bit
ACPI
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override or processor
Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits
are cleared by RTCRST#.
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Datasheet